The present invention relates generally to semiconductor processing methods of forming floating gate transistors and to floating gate transistors.
Increased device performance is a continuing goal of efforts in advancing the semiconductor arts. For nonvolatile memory devices such as a programmable read only memory (PROM), increased device performance has been realized by improvements in both the programmability and erasure of the stored information. For example, early PROM devices were erased using exposure of the integrated circuit to ultra-violet light for a period of time on the order of twenty minutes to erase the entirety of the stored memory. Newer devices such as an electrically erasable programmable read only memory (EEPROM), as the name implies, are erasable using an electrical signal. While such EEPROM devices have reduced erasure time, the electrical signal employed for erasing is at a higher than normal voltage that results in a limiting of the number of times the device can be erased and reprogrammed. In addition, generally, erasing such EEPROM devices results in all stored information being erased.
More recently developed devices such as the flash-EEPROM device have provided the ability to use normal electrical voltages for erasure as well as providing for partial erasures. As such erasures and subsequent reprogramming are possible at essentially xe2x80x9cnormalxe2x80x9d semiconductor speeds, flash-EEPROM devices are also generally referred to as a flash random access memory device or flash-RAM. With the increased performance of the flash-RAM, it has become desirable to increase the density of the memory storage units which generally encompass both a floating gate and a control gate for each unit. One problem with forming devices with such increased density has been the forming of the floating gate structures using generally known photolithographic methods. Therefore it would be desirable to provide alternative methods for forming floating gate transistor structures as well as the structures formed employing such methods.
Exemplary embodiments of forming floating gate transistor structures in accordance with the present invention employ providing a substrate encompassing semiconductive material. A first layer is formed over the semiconductive material. At least one pair of spaced shallow trench isolation (STI) structures are formed extending through the first layer and into the semiconductive material, and at least a portion of the first layer between the spaced STI structures is removed effective to form a recess there between. The recess is at least partially filled by forming a conductive floating gate material therein and a control gate is formed operatively over the conductive floating gate material to form the floating gate transistor.